Not Applicable.
1. Field of the Invention
The present invention is directed generally to a buffer and, more particularly, to a buffer with adjustable slew rate and a method of providing an adjustable slew rate.
2. Description of the Background
Slew rate is a ratio of a ripe or fall in voltage to the amount of time that rise or fall takes. Consequently, slew rate is a quantity which can be a controlling factor in the performance characteristics of a device. A device having a low slew rate can degrade the performance and speed of a system containing the device, while a device having a high slew rate may not allow the system to react to changes in the state of the device, and thereby cause breakdown of the system.
Those effects of slew rate have led manufacturers of processors and computer systems, such as Intel, to specify performance windows into which device slew rate characteristics must fall in order to properly operate with their processors and computer systems. However, process variations between different fabrication processes can cause large variations in device characteristics, such as drain to source current. For example, drain to source current characteristics for a p-channel fabrication have been shown to vary as much as 48%, depending upon the manufacturing process used to create the device. Such variations in device characteristics make it difficult, if not impossible, to insure that a device will exhibit slew rate characteristics within the performance window as set forth by the computer manufacturer.
Therefore, the need exists for a buffer that allows adjustment of slew rate characteristics after a circuit or device has been manufactured.
The present invention is directed to an apparatus for adjusting slew rate. The apparatus includes a current driver having an input terminal and an enable circuit connected to the input terminal to selectively enable the current driver.
In one embodiment of the present invention, the current driver includes an input terminal and the enable circuit includes a memory element, the state of which is used to activate the enable signal, a read circuit which reads the state of the memory element, a latch which latches the signal from the read circuit, and an output circuit connected to the input terminal of the current driver and which provides a signal which selectively enables the current driver.
The present invention may be used to adjust the slew rate of a device, such as a memory device or a processor device. The present invention may also be used to adjust the slew rate of a system including a device, such as a memory device or a processor.
The present invention is also directed to a method of adjusting slew rate of a device including a current driver. The method includes providing a memory element having a state and providing to the current driver an enable signal indicative of the state of the memory element.
The present invention solves problems experienced with the prior art, such as the inability to adjust slew rate to overcome fabrication process variations, because the programmable capabilities of the present invention allow adjustment of the slew rate. That adjustment will allow buffers to meet the specifications of PC manufacturers in PC related applications, thereby allowing buffers to advance to meet the needs of next-generation PC technology.
Those and other advantages and benefits of the present invention will become apparent from the description of the preferred embodiments hereinbelow.